The Two-stage or Miller OTA

Design

Christian Enz

Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

# Initialization¶

# Introduction¶

Schematic of the Miller OTA.

This notebook presents the design of the basic two-stage or Miller OTA shown in the above figure. In this Notebook we will focus on minimizing the power consumption at the cost of a larger area compared to the minimum area Notebook.

# Process Parameters¶

All the parameters required for the design are given below. They correspond to a generic $0.18\,\mu m$ process.

    Main physical parameters:
    ═════════════════════════

$T =$ 300 K
$U_T =$ 25.875 mV

    Main process parameters for TSMC 0.18um:
    ════════════════════════════════════════

$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm

    nNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 39 nm
$\Delta L =$ −76 nm

    pNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

# OTA Specifications¶

The OTA specifications are included in the file specs.py. For this design, they are focused on the gain-bandwidth product and dc gain without any constraints on the flicker noise or corner frequency.

$A_{dc} =$ 100 dB
$GBW =$ 1 MHz
$C_L =$ 1 pF
$V_{os,max} =$ 10 mV
$PM =$ 60 $^{\circ}$

# Miller OTA Sizing¶

## Sizing procedure¶

If the DC gain of the second stage $G_{m2}/G_2$ can be assumed to be much larger than 1, the dominant pole can be approximated by \begin{equation*} \omega_{p1} = |p_1| \cong \frac{G_1\,G_2}{G_{m2}\,C_c}. \end{equation*}

Since $C_1$ is a parasitic capacitance, it is reasonable to consider that it is much smaller than the compensation capacitance $C_c$ and the load capacitance $C_L$. Both assumptions $C_1 \ll C_c$ and $C_1 \ll C_L$ lead to the following approximation of the non-dominant pole \begin{equation*} \omega_{p2} = |p_2| \cong \frac{G_{m2}}{C_L}. \end{equation*} In the design procedure we need to make sure that the non-dominant pole $\omega_{p2}$ and the RHP zero $\omega_z$ are sufficiently larger than the $GBW$ in order to secure enough phase margin. The ratio of the non-dominant pole and the zero to the unity gain frequency is given by \begin{align*} \frac{\omega_{p2}}{\omega_u} &= \frac{G_{m2}}{G_{m1}} \cdot \frac{C_c}{C_L},\\ \frac{\omega_z}{\omega_u} &= \frac{G_{m2}}{G_{m1}} \end{align*} and hence \begin{align*} \frac{\omega_{p2}}{\omega_u} &= \frac{\omega_z}{\omega_u} \cdot \frac{C_c}{C_L},\\ \frac{\omega_z}{\omega_{p2}} &= \frac{C_L}{C_c}. \end{align*} The unity gain frequency $\omega_u$, non-dominant pole $\omega_{p2}$ and zero $\omega_z$ need to satisfy \begin{equation*} \omega_u < \omega_{p2} < \omega_z, \end{equation*} or \begin{equation*} 1 < \frac{\omega_{p2}}{\omega_u} < \frac{\omega_z}{\omega_u}. \end{equation*} This translates to the following inequality \begin{equation*} 1 < \frac{C_L}{C_c} < \frac{G_{m2}}{G_{m1}}. \end{equation*} This means that the compensation capacitance $C_c$ should stay smaller than the load capacitance $C_L$ and that the ratio of the transconductance of M2 to that of M1 should be larger than $C_L/C_c$.

Usually the compensation capacitance $C_c$ is a fraction of the load capacitance $C_L$ which can be determined from the specified phase margin $PM$ which is given by \begin{equation*} PM = \arctan\left(\frac{\omega_u}{\omega_z}\right)+\arctan\left(\frac{\omega_u}{\omega_{p2}}\right)-\frac{\pi}{2}. \end{equation*} For example if

$\omega_{p2}/\omega_u =$ 4
$\omega_z/\omega_{p2}=$ 2
$\omega_z/\omega_u =$ 8
$PM =$ 68.839 $^{\circ}$

which is usually more than sufficient. However we need to account for parasitic capacitances which add to the load capacitance and reduce the non-dominant pole. Therefore a good trade-off to start the design and achieve a sufficient $PM$ (typically larger than 45 degree) is to choose $\omega_{p2}= 4\,\omega_u$ and $\omega_z = 2\,\omega_{p2} = 8\,\omega_u$. This results in choosing $C_c=C_L/2$

$C_c =$ 500 fF

It is important to note that choosing $\omega_z/\omega_u=G_{m2}/G_{m1}=8$ for securing enough phase margin has a direct impact on the power consumption. Indeed, if we assume that both M1a-M1b and M2 are biased in weak inversion for maximizing the current efficiency, then $G_{m1}=I_{b1}/(n_n\,U_T)$ and $G_{m2}=I_{b2}/(n_p\,U_T)$. Assuming that $n_n=n_p$, $G_{m2}/G_{m1}=I_{b2}/I_{b1}=8$. This means that the bias current of M2 is 8 times larger than that of M1a-M1b! The total current consumption, without accounting for the current flowing in M3a and M5a, is then $I_{tot} = 2 I_{b1} + I_{b2} = 10\,I_{b1}$. We can express the minimum total current consumption in terms of the gain-bandwidth product $GBW$ as $I_{tot} \cong 10\,n U_T \cdot C_c \cdot GBW = 5\,n U_T \cdot C_L \cdot GBW$. This can be compared to the total current consumption of the symmetrical cascode OTA $I_{tot} = 4\,n U_T \cdot C_L \cdot GBW$. We deduce that for the same gain-bandwidth product $GBW$ and load capacitance $C_L$, the Miller OTA consumes about 25\% more current than the symmetrical cascode OTA.

Knowing $C_c$ we can now derive $G_{m1}$ from the $GBW$

$G_{m1} =$ 3.142 µA/V

The minimum current to achieve this transconductance and GBW assuming that M1a-M1b are biased in weak inversion is given by

$I_{b1,min} =$ 103 nA

We can already estimate the total current consumption, ignoring the current drawn by M3a and M5a as

$I_{tot,min} =$ 1.033 µA

and we can set $G_{m2}$

$G_{m2} =$ 25.133 µA/V

We can now size M1a-M1b, which should be biased in weak inversion in order to minimize the input-referred offset. Let's set the inversion coefficient of M1a-M1b to

$IC_1 =$ 0.1

The required bias current for M1a-M1b is then given by

$I_{b1,min} =$ 112.815 nA

Let's take some margin and set $I_{b1}$ to

$I_{b1} =$ 130 nA

The transconductance can be recalculated from the $G_m/I_D$ function as

$G_{m1} =$ 3.620 µA/V

The corresponding $GBW$ is then given by

$GBW =$ 1.152 MHz

which is slightly higher than the target specification offering some margin.

The aspect ratio $W_1/L_1$ is then given by

$I_{spec1} =$ 1 µA
$\frac{W_1}{L_1} =$ 1.8

The length will be calculated below from the specifications on the DC gain.

The biasing of M2 should however be compatible with that of M4a-M4b. The latter should be biased in strong inversion for better matching but also to achieve a transconductance $G_{m4}$ smaller than $G_{m1}$ in order to reduce its noise contribution. So we will first size M4a-M4b.

The source and drain voltage of M4a should be set as low as possible for achieving a maximum common mode input voltage still keeping M1a in saturation. For a maximum input common-mode voltage given by

$V_{ic,max} =$ 1.3 V
$V_{GS1} =$ 382 mV
$V_{DSsat1} =$ 105 mV
$V_{SG4} =$ 778 mV

We set $V_{SG4}$ to

$V_{SG4} =$ 800 mV

this corresponds to an inversion coefficient given by

$IC_4 =$ 24.8

We will choose

$IC_4 =$ 25

The saturation voltage of M4a-M4b is then given by

$V_{DSsat4} =$ 364 mV

The transconductance of M4a-M4b is then given by

$I_{spec4} =$ 5.2 nA
$\frac{W_4}{L_4} =$ 3.0e-02
$G_{m4} =$ 696 nA/V

We will use the specification on the DC gain to set the length of the various transistors. The DC gain is given by

$A_{dc} =$ 1e+05

We can distribute the DC gain equally among the first and second stage

$A_{dc1} =$ 316

The conductance at node 1 $G_1$ is then given by

$G_1 =$ 11.4 nA/V

The conductance $G_1$ depends on the output conductances of M1b and M4b $G_1 = G_{ds1b} + G_{ds4b}$. We now can split it half-half between M1b and M4b. The length of M1b is then estimated as

$L_1 =$ 1.140 µm

From which we now get the width

$W_1 =$ 2.07 µm

Similarly for M4 we get the length from

$L_4 =$ 1.14 µm

from which we get the width

$W_4 =$ 30 nm

which is smaller than the minimum width. We then set $W_4$ to the minimum width

$W_4 =$ 200 nm
$L_4 =$ 6.66 µm

We now set $G_{m2}$ 8 times the recalculated value of $G_{m1}$

$G_{m2} =$ 29.0 µA/V

To size M2, we first calculate the second stage voltage gain

$A_{dc2} =$ 316

The sizing of M2 is tricky. Indeed, ideally, for low-power we would choose to bias M2 in weak inversion for a maximum current efficiency. This will set the bulk-to-gate voltage of M2 to about $V_{T0p}$. On the other hand the quiescent voltage at node 1 (gate of M2) is equal to that of node 4 which is equal to $V_{BG4}$. Having chosen to bias M4a-M4b in strong inversion results in $V_{BG4}$ to be larger than $V_{T0p}$ by the overdrive voltage of M4a-M4b $V_{BG4}-V_{T0p}$. Therefore th bulk-to-gate voltage is actually larger than $V_{T0p}$ and since M2 is bias in weak inversion with a current imposed by the current source M5b which is much smaller than the current that M2 would carry with such a large gate voltage. The only degree of freedom left is the source-to-drain voltage of M2 which becomes very small to reduce the current to the level of the bias current imposed by M5b. M2 is therefore biased in the linear region with a source-to-drain voltage close to zero. That means that the output voltage will saturate to $V_{DD}$. In order to bring the output voltage back into the gain region (for example equal to the input common-mode voltage), a differential input voltage needs to be applied which actually corresponds to a systematic offset which can be quite large. If the OTA is used in a closed-loop configuration, which is usually the case, this offset voltage should not be a problem.

A more important consequence of biasing M2 in weak inversion is that this results in a very large transistor increasing the parasitic capacitance at node 1 and therefore reducing the non-dominant pole and hence the phase margin. Increasing the inversion coefficient $IC_2$ reduces the area of M2 gate area at the cost of less efficiency.

To find what is the optimum inversion coefficient for M2 that minimizes the parasitic capacitance at node 1 and secures enough phase margin, we can plot its area versus $IC_2$ for a given value of $G_{m2}$ and of the second stage gain $A_{dc2}$.

    IC2min = 2.089
    WL2min = 25.828 um^2

We observe that there is an optimum value of $IC_2$ for which the area of M2is minimum. This optimum $IC$ is in the moderate inversion. Let's now set $IC_2$ to this optimum value.

$IC_2 =$ 2.1

The current can be derived from $G_{m2}$ and the $G_m/I_D$ ratio as

$I_{b2} =$ 1.986 µA

which is about twice the minimum value we would get if M2 is biased in weak inversion.

$I_{b2} =$ 1.986 µA
$I_{b2}/I_{b2,min} =$ 2.0

We round it to

$I_{b2} =$ 2.0 µA

We can now recompute $G_{m2}$

$G_{m2} =$ 29.2 µA/V
$G_{m2}/G_{m1} =$ 8.1

We can now derive the specific current $I_{spec}$ and $W/L$ as

$I_{spec2} =$ 957.260 nA
$\frac{W_2}{L_2} =$ 5.5

The conductance $G_2$ at the output node is then given by

$G_2 =$ 92 nA/V

which we split equally among M2 and M5b leading to

$L_2 =$ 2.2 µm

From which we get the width

$W_2 =$ 12.00 µm

Similarly for M5b we get

$L_5 =$ 2.17 µm

To finalize the sizing of M5b we can set its saturation voltage to

$V_{DSsat5} =$ 300 mV

which corresponds to an inversion coefficient given by

$IC_5 =$ 29.6

which we round to

$IC_5 =$ 30
$V_{DSsat5} =$ 302 mV

Having $I_D$ and $IC$ we can get the $W/L$

$I_{spec5} =$ 67 nA
$\frac{W_5}{L_5} =$ 0.093
$W_5 =$ 200.00 nm

which by chance is equal to $W_{min}$.

We now need to size M3a-M3b according to the minimum common-mode input voltage to be handled

$V_{DSsat3} =$ 318 mV

We can derive the corresponding $IC$ as

$IC_3 =$ 33.7

We choose

$IC_3 =$ 30

From $I_{b1}$ and $IC_3$ we can get the $W/L$ ratio

$I_{spec3} =$ 8.667 nA
$\frac{W_3}{L_3} =$ 1.212e-02

We need to set $W_3$ to the minimum width

$W_3 =$ 200 nm
$L_3 =$ 16.5 µm

The sizing process is finalized.

## Summary¶

### Specifications¶

The specifications are recalled below.

| Name | Value
--- | --- | ---
0 | AdcdB | 1.000000e+02
1 | GBWmin | 1.000000e+06
2 | CL | 1.000000e-12
3 | Vosmax | 1.000000e-02
4 | PMdeg | 6.000000e+01

### Bias¶

The bias information are summarized below.

| Name | Value
--- | --- | ---
0 | VDD | 1.800000e+00
1 | Ib1 | 1.300000e-07
2 | Ib2 | 2.000000e-06
3 | Cc | 5.000000e-13

### Transistor sizes¶

The transistor sizes are summarized below.

| Type | Function | W | L | ID
--- | --- | --- | --- | --- | ---
M1a | n | DP | 2.36E-06 | 1.30E-06 | 1.30E-07
M1b | n | DP | 2.36E-06 | 1.30E-06 | 1.30E-07
M2 | p | CS | 8.02E-06 | 1.45E-06 | 2.00E-06
M3a | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07
M3b | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07
M4a | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07
M4b | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07
M5a | n | CM | 1.40E-07 | 1.45E-06 | 2.00E-06
M5b | n | CM | 1.40E-07 | 1.45E-06 | 2.00E-06

| Type | Function | W | L | ID | W/L | Ispec | IC | VP-VS | VG-VT0 | ... | CGSe | CGDe | CGBe | CBSe | CBDe | CGS | CGD | CGB | CBS | CBD
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 2.07E-06 | 1.14E-06 | 1.30E-07 | 1.82E+00 | 1.30E-06 | 1.00E-01 | -5.71E-02 | -4.49E-02 | ... | 7.59E-16 | 7.59E-16 | 0.00E+00 | 3.64E-15 | 3.64E-15 | 2.39E-15 | 7.59E-16 | 3.91E-15 | 4.09E-15 | 3.64E-15
M1b | n | DP | 2.07E-06 | 1.14E-06 | 1.30E-07 | 1.82E+00 | 1.30E-06 | 1.00E-01 | -5.71E-02 | -4.49E-02 | ... | 7.59E-16 | 7.59E-16 | 0.00E+00 | 3.64E-15 | 3.64E-15 | 2.39E-15 | 7.59E-16 | 3.91E-15 | 4.09E-15 | 3.64E-15
M2 | p | CS | 1.20E-05 | 2.17E-06 | 2.00E-06 | 5.53E+00 | 9.57E-07 | 2.09E+00 | 5.40E-02 | 4.14E-02 | ... | 3.94E-15 | 3.94E-15 | 0.00E+00 | 3.62E-14 | 3.62E-14 | 9.66E-14 | 3.94E-15 | 2.98E-14 | 6.46E-14 | 3.62E-14
M3a | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07 | 1.21E-02 | 8.67E-09 | 3.00E+01 | 3.00E-01 | 2.36E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 9.98E-15 | 9.98E-15 | 1.68E-14 | 7.33E-17 | 2.37E-15 | 1.45E-14 | 9.98E-15
M3b | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07 | 1.21E-02 | 8.67E-09 | 3.00E+01 | 3.00E-01 | 2.36E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 9.98E-15 | 9.98E-15 | 1.68E-14 | 7.33E-17 | 2.37E-15 | 1.45E-14 | 9.98E-15
M4a | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07 | 3.00E-02 | 5.20E-09 | 2.50E+01 | 2.73E-01 | 2.09E-01 | ... | 6.57E-17 | 6.57E-17 | 0.00E+00 | 4.90E-15 | 4.90E-15 | 6.76E-15 | 6.57E-17 | 1.07E-15 | 6.95E-15 | 4.90E-15
M4b | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07 | 3.00E-02 | 5.20E-09 | 2.50E+01 | 2.73E-01 | 2.09E-01 | ... | 6.57E-17 | 6.57E-17 | 0.00E+00 | 4.90E-15 | 4.90E-15 | 6.76E-15 | 6.57E-17 | 1.07E-15 | 6.95E-15 | 4.90E-15
M5a | n | CM | 2.00E-07 | 2.17E-06 | 2.00E-06 | 9.22E-02 | 6.59E-08 | 3.03E+01 | 3.02E-01 | 2.38E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 1.38E-15 | 1.38E-15 | 2.28E-15 | 7.33E-17 | 3.11E-16 | 1.98E-15 | 1.38E-15
M5b | n | CM | 2.00E-07 | 2.17E-06 | 2.00E-06 | 9.22E-02 | 6.59E-08 | 3.03E+01 | 3.02E-01 | 2.38E-01 | ... | 7.33E-17 | 7.33E-17 | 0.00E+00 | 1.38E-15 | 1.38E-15 | 2.28E-15 | 7.33E-17 | 3.11E-16 | 1.98E-15 | 1.38E-15

9 rows × 32 columns

# OTA Characteristics¶

## Sizing summary¶

### Process parameters¶

    Main physical parameters:
    ═════════════════════════

$T =$ 300 K
$U_T =$ 25.875 mV

    Main process parameters for TSMC 0.18um:
    ════════════════════════════════════════

$V_{DD} =$ 1.8 V
$C_{ox} =$ 8.443 $\frac{{fF}}{{\mu m^2}}$
$W_{min} =$ 200 nm
$L_{min} =$ 180 nm

    nNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.27
$I_{spec\Box} =$ 715 nA
$V_{T0} =$ 455 mV
$L_{sat} =$ 26 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.366 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.000 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.200 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 8.1e-24 J
$AF =$ 1.0
$\rho =$ 5.794e-02 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 600 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 39 nm
$\Delta L =$ −76 nm

    pNMOS parameters:
    ═════════════════
    Long-channel sEKV parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$n =$ 1.31
$I_{spec\Box} =$ 173 nA
$V_{T0} =$ 445 mV
$L_{sat} =$ 36 nm
$\lambda =$ 20 $\frac{{V}}{{\mu m}}$

    Overlap capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_{GDo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GSo} =$ 0.329 $\frac{{fF}}{{\mu m}}$
$C_{GBo} =$ 0.000 $\frac{{fF}}{{\mu m}}$

    Junction capacitances:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$C_J =$ 1.121 $\frac{{fF}}{{\mu m^2}}$
$C_{JSW} =$ 0.248 $\frac{{fF}}{{\mu m}}$

    1/f noise parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$K_F =$ 6.8e-23 J
$AF =$ 1.0
$\rho =$ 4.828e-01 $\frac{{V \cdot m^2}}{{A \cdot s}}$

    Matching parameters:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$A_{VT} =$ 5 $mV \cdot \mu m$
$A_{\beta} =$ 1 $\% \cdot \mu m$

    Source and drain sheet resistance:
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$R_{sh} =$ 2386 $\frac{\Omega}{\mu m}$

    Channel width and length corrections
    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

$\Delta W =$ 54 nm
$\Delta L =$ −72 nm

### Specifications¶

| Value
--- | ---
Name |
AdcdB | 1.00E+02
GBWmin | 1.00E+06
CL | 1.00E-12
Vosmax | 1.00E-02
PMdeg | 6.00E+01

$A_{dc} =$ 100 dB
$GBW =$ 1 MHz
$C_L =$ 1 pF
$V_{osmax} =$ 10 mV
$PM =$ 60 deg

### Bias information¶

| Value
--- | ---
Name |
VDD | 1.80E+00
Ib1 | 1.30E-07
Ib2 | 2.00E-06
Cc | 5.00E-13

$I_{b1} =$ 130 nA
$I_{b2} =$ 2.0 µA
$C_c =$ 500 fF

### Transistors information¶

| Type | Function | W | L | ID | W/L | Ispec | IC | VP-VS | VG-VT0 | ... | CGSe | CGDe | CGBe | CBSe | CBDe | CGS | CGD | CGB | CBS | CBD
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
M1a | n | DP | 2.07E-06 | 1.14E-06 | 1.30E-07 | 1.82E+00 | 1.30E-06 | 1.00E-01 | -5.71E-02 | -4.49E-02 | ... | 7.59E-16 | 7.59E-16 | 0 | 3.64E-15 | 3.64E-15 | 2.39E-15 | 7.59E-16 | 3.91E-15 | 4.09E-15 | 3.64E-15
M1b | n | DP | 2.07E-06 | 1.14E-06 | 1.30E-07 | 1.82E+00 | 1.30E-06 | 1.00E-01 | -5.71E-02 | -4.49E-02 | ... | 7.59E-16 | 7.59E-16 | 0 | 3.64E-15 | 3.64E-15 | 2.39E-15 | 7.59E-16 | 3.91E-15 | 4.09E-15 | 3.64E-15
M2 | p | CS | 1.20E-05 | 2.17E-06 | 2.00E-06 | 5.53E+00 | 9.57E-07 | 2.09E+00 | 5.40E-02 | 4.14E-02 | ... | 3.94E-15 | 3.94E-15 | 0 | 3.62E-14 | 3.62E-14 | 9.66E-14 | 3.94E-15 | 2.98E-14 | 6.46E-14 | 3.62E-14
M3a | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07 | 1.21E-02 | 8.67E-09 | 3.00E+01 | 3.00E-01 | 2.36E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 9.98E-15 | 9.98E-15 | 1.68E-14 | 7.33E-17 | 2.37E-15 | 1.45E-14 | 9.98E-15
M3b | n | CM | 2.00E-07 | 1.65E-05 | 2.60E-07 | 1.21E-02 | 8.67E-09 | 3.00E+01 | 3.00E-01 | 2.36E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 9.98E-15 | 9.98E-15 | 1.68E-14 | 7.33E-17 | 2.37E-15 | 1.45E-14 | 9.98E-15
M4a | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07 | 3.00E-02 | 5.20E-09 | 2.50E+01 | 2.73E-01 | 2.09E-01 | ... | 6.57E-17 | 6.57E-17 | 0 | 4.90E-15 | 4.90E-15 | 6.76E-15 | 6.57E-17 | 1.07E-15 | 6.95E-15 | 4.90E-15
M4b | p | CM | 2.00E-07 | 6.66E-06 | 1.30E-07 | 3.00E-02 | 5.20E-09 | 2.50E+01 | 2.73E-01 | 2.09E-01 | ... | 6.57E-17 | 6.57E-17 | 0 | 4.90E-15 | 4.90E-15 | 6.76E-15 | 6.57E-17 | 1.07E-15 | 6.95E-15 | 4.90E-15
M5a | n | CM | 2.00E-07 | 2.17E-06 | 2.00E-06 | 9.22E-02 | 6.59E-08 | 3.03E+01 | 3.02E-01 | 2.38E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 1.38E-15 | 1.38E-15 | 2.28E-15 | 7.33E-17 | 3.11E-16 | 1.98E-15 | 1.38E-15
M5b | n | CM | 2.00E-07 | 2.17E-06 | 2.00E-06 | 9.22E-02 | 6.59E-08 | 3.03E+01 | 3.02E-01 | 2.38E-01 | ... | 7.33E-17 | 7.33E-17 | 0 | 1.38E-15 | 1.38E-15 | 2.28E-15 | 7.33E-17 | 3.11E-16 | 1.98E-15 | 1.38E-15

9 rows × 32 columns

## Open-loop gain¶

$A_{dc1} =$ 542
$A_{dc2} =$ 316
$A_{dc} =$ 1.715e+05
$A_{dc1} =$ 54.7 dB
$A_{dc2} =$ 50.0 dB
$A_{dc} =$ 104.7 dB
$C_{GS2} =$ 96.6 fF
$C_{GB2} =$ 29.8 fF
$C_{BD4} =$ 4.9 fF
$C_{BD1} =$ 3.6 fF
$C_{GD1} =$ 758.7 aF
$C_1 =$ 135.7 fF
$C_{BD2} =$ 36.222 fF
$C_{BD5} =$ 1.382 fF
$C_L =$ 1.000 pF
$C_2 =$ 1.038 pF
$GBW =$ 1 MHz (spec)
$GBW = G_{m1}/C_c =$ 1.152 MHz
$GBW =$ 1.097 MHz (theory)
$f_{p1} =$ 6.7 Hz
$f_{p2} =$ 3.2 MHz
$f_z =$ 9.3 MHz

We can plot the magnitude and phase of the open-loop gain.

    PGBW = −115.719 deg
    PM = 64.281 deg

We can see that all the specifications are met.

## Input-referred noise¶

We now can estimate the input-referred noise PSD.

$G_{m1} =$ 3.620 µA/V
$G_{m2} =$ 29.163 µA/V
$G_{m4} =$ 696.227 nA/V
$G_{m5} =$ 10.080 µA/V
$G_{m1}/G_{m4} =$ 5.2
$G_{m2}/G_{m5} =$ 2.893
$2 G_{m1} G_{m2}/G_1^2 =$ 4.7e+06
$\gamma_{n1} =$ 0.653
$\gamma_{n2} =$ 0.763
$\gamma_{n4} =$ 0.831
$\gamma_{n5} =$ 0.812
$\eta_{th} =$ 0.245
$2\gamma_{n1} =$ 1.307
$\gamma_{neq} =$ 1.627
$R_{nth} =$ 449 kOhm
$\sqrt{S_{ninth}} =$ 86.3 $\frac{nV}{\sqrt{Hz}}$
$10 \cdot \log(S_{ninth}) =$ -141.3 $\frac{dBv}{\sqrt{Hz}}$
$(G_{m1}/G_{m4})^2 =$ 27.0
$(G_{m1}/G_1)^2 =$ 2.9e+05
$(G_{m2}/G_{m5})^2 =$ 8.371
$\frac{W_1 \cdot L_1}{W_4 \cdot L_4} =$ 1.8
$\frac{W_1 \cdot L_1}{W_2 \cdot L_2} =$ 9.1e-02
$\frac{W_1 \cdot L_1}{W_5 \cdot L_5} =$ 5.437
$\eta_{fl} =$ 0.546
$f_k =$ 168.9 kHz

We can plot the input-reffered noise

## Input-referred offset voltage¶

The variance of the input-referred offset is given by \begin{equation*} \sigma_{V_{os}}^2 = \sigma_{VT1}^2 + \left(\frac{G_{m3}}{G_{m1}}\right)^2 \cdot \sigma_{VT3}^2 + \left(\frac{I_{b1}}{G_{m1}}\right)^2 \cdot \left(\sigma_{\beta 1}^2 + \sigma_{\beta 3}^2\right) \end{equation*} where \begin{align*} \sigma_{VT1}^2 &= \frac{A_{VTn}^2}{W_1 L_1},\\ \sigma_{\beta 1}^2 &= \frac{A_{\beta n}^2}{W_1 L_1},\\ \sigma_{VT3}^2 &= \frac{A_{VTp}^2}{W_3 L_3},\\ \sigma_{\beta 3}^2 &= \frac{A_{\beta p}^2}{W_3 L_3},\\ \end{align*}

$\sigma_{VT1} =$ 3.255 mV
$\sigma_{VT4} =$ 4.332 mV
$\sqrt{\sigma_{VT1}^2+(G_{m4}/G_{m1})^2\,\sigma_{VT4}^2} =$ 3.360 mV
$\sigma_{\beta1} =$ 0.651 %
$\sigma_{\beta4} =$ 0.866 %
$\sqrt{(I_{b1}/G_{m1})^2\,(\sigma_{\beta1}+\sigma_{\beta4})} =$ 389.215 µV
$\sigma_{Vos} =$ 3.263 mV (contribution of M1a-M1b)
$\sigma_{Vos} =$ 2.307 mV (contribution of M1a only)
$\sigma_{Vos} =$ 889.476 µV (contribution of M4a-M4b)
$\sigma_{Vos} =$ 628.955 µV (contribution of M4a only)
$\sigma_{Vos} =$ 3.382 mV

We see that the random part of the input-referred offset voltage is dominated by the contribution of the differential pair.

## Power consumption¶

The total power consumption (without the current sources) is given by

$I_{tot} =$ 2.260 µA
$P =$ 4.068 µW

We can compare the current and power consumption of the Miller OTA to the symmetrical cascode OTA

$I_{sym cas OTA} =$ 1.0 µA
$I_{Miller OTA}/I_{sym cas OTA} =$ 2.260

The current and power consumption of the Miller OTA is 2.26 times larger than that of the symmetrical cascode OTA for the same specifications and performance.

# Conclusion¶

This notebook presented the detailed design of the basic two-stage or Miller OTA for a given set of specifications. We see that the power consumption of the two-stage OTA is almost 10 times that of the symmetrical OTA for the same open-loop gain response, noise and offset specification. This design is verified by simulation in the Verification Notebook.